SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 55

• Manufacturer Part Number: SI4431-A0-FM
• Description: IC TXRX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-A0-FM

• Package / Case: 20-QFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 28 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1633-5

8. Auxiliary Functions
8.1. Smart Reset
The Si4431 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a
classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce reliable
reset signal in any circumstances. Reset will be initiated if any of the following conditions occur:




The reset will initialize all registers to their default values. The reset signal is also available for output and use by
the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by default on
GPIO_1.
Initial power on, when VDD starts from 0V: reset is active till VDD reaches V
When VDD decreases below V
A software reset via “Register 08h. Operating Mode and Function Control 2,” on page 92: reset is active for time
T
On the rising edge of a VDD glitch when the supply voltage exceeds the following time functioned limit:
Release Reset Voltage
Power-On VDD Slope
Low VDD Limit
Software Reset Pulse
Threshold Voltage
Reference Slope
VDD Glitch Reset Pulse
SWRST
Parameter
VDD starts to rise
0.4V
LD
Figure 23. POR Glitch Parameters
TSWRST
for any reason: reset is active till VDD reaches V
Symbol
SVDD
VTSD
VRR
VDD(t)
VLD
TP
k
Table 22. POR Parameters
t=0,
Preliminary Rev. 0.4
VDD nom.
Also occurs after SDN, and
VLD<VRR is guaranteed
tested VDD slope region
initial power on
reset:
Vglitch>=0.4+t*0.2V/ms
Comment
showing glitch
actual VDD(t)
Reset
0.4V+t*0.2V/ms
T
P
reset limit:
RR
t
0.85
0.03
Min
0.7
50
(see table);
5
RR
again;
Typ
1.3
0.4
0.2
15
1
Max
1.75
300
470
1.3
40
Si4431
V/ms
V/ms
Unit
ms
us
V
V
V
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