SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 82

• Manufacturer Part Number: SI4431-A0-FM
• Description: IC TXRX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-A0-FM

• Package / Case: 20-QFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 28 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1633-5

4C-4E
Add
3D
5C
5D
6C
6D
7C
7D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7E
7F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
Si4431
82
RC Oscillator Coarse Calibration/Override
Turn Around and 15.4 Length Compliance
Invalid Preamble Threshold and PA Misc
Chargepump Current Trimming/Override
RC Oscillator Fine Calibration/Override
GFSK FIR Filter Coefficient Address
Frequency Hopping Channel Select
Channel Filter Coefficient Address
GFSK FIR Filter Coefficient Value
Channel Filter Coefficient Value
Crystal Oscillator / Control Test
Frequency Hopping Step Size
Nominal Carrier Frequency 1
Nominal Carrier Frequency 0
Modulation Mode Control 1
Modulation Mode Control 2
VCO Calibration / Override
Deltasigma ADC Tuning 1
Deltasigma ADC Tuning 2
Divider Current Trimming
Received Packet Length
Block Enable Override 1
Transmit Packet Length
Block Enable Override 2
Block Enable Override 3
Frequency Band Select
VCO Current Trimming
Miscellaneous Settings
LDO Control Override
Frequency Deviation
Received Header 3
Received Header 2
Received Header 1
Received Header 0
Frequency Offset 1
Frequency Offset 2
Transmit Header 0
Calibration Control
TX FIFO Control 1
TX FIFO Control 2
LDO Level Setting
Chargepump Test
TX Ramp Control
Header Enable 3
Header Enable 2
Header Enable 1
Header Enable 0
RX FIFO Control
Synthesizer Test
Check Header 3
Check Header 2
Check Header 1
Check Header 0
Analog Test Bus
AGC Override 1
AGC Override 2
Function/Desc
Digital Test Bus
PLL Tune Time
TX Data Rate 1
TX Data Rate 0
ADC8 Control
FIFO Access
Modem Test
TX Power
Table 28. Register Descriptions (Continued)
vcocalov/vcdone
txcorboosten
txcurboosten
15.4 Length
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
agcovpm
chhd[31]
chhd[23]
chhd[15]
hden[31]
hden[23]
hden[15]
rxplen[7]
Reserved
cpcurr[1]
pklen[7]
rxhd[31]
rxhd[23]
rxhd[15]
chhd[7]
hden[7]
bcrfbyp
txdr[15]
pwst[2]
txhd[7]
rxhd[7]
enspor
trclk[1]
fhch[7]
fifod[7]
pllts[4]
enfrdv
txdr[7]
dsmdt
enmix
adcrst
pfdrst
rccov
enovr
fc[15]
fhs[7]
ends
rcfov
fd[7]
fo[7]
fc[7]
D7
xtalstarthalf
vcocorrov
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
vcocal[6]
Preliminary Rev. 0.4
chhd[30]
chhd[22]
chhd[14]
hden[30]
hden[22]
hden[14]
rxplen[6]
ensctest
txmod[2]
fbdiv_rst
cpcurr[0]
enrefdac
rxhd[30]
rxhd[22]
rxhd[14]
agcslow
pklen[6]
vcotype
chhd[6]
hden[6]
slicfbyp
endv31
txdr[14]
rxhd[6]
fbdivhc
pwst[1]
txhd[6]
pllts[3]
enbias
trclk[0]
fhch[6]
fifod[6]
enldet
txdr[6]
enxtal
enlna
rcc[6]
sbsel
fc[14]
fhs[6]
rcf[6]
fd[6]
fo[6]
fc[6]
D6
inv_pre_th[3] inv_pre_th[2] inv_pre_th[1] inv_pre_th[0] Ido_pa_boost
Reserved
adccaldone
lnacomp[3]
txdtrtscale
cpforceup
vcocorr[3]
Reserved
Reserved
chfilval[5]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
envcoldo
txaethr[5]
chhd[29]
chhd[21]
chhd[13]
hden[29]
hden[21]
hden[13]
rxplen[5]
txmod[1]
cpcorrov
d3trim[1]
vcocal[5]
dtmod[1]
txafthr[5]
rxafthr[5]
rxhd[29]
rxhd[21]
rxhd[13]
pklen[5]
enoloop
chhd[5]
hden[5]
adc8[5]
txdr[13]
pwst[0]
firval[5]
txhd[5]
rxhd[5]
enmx3
fhch[5]
fifod[5]
pllts[2]
dttype
enpga
endv2
enadc
agcen
txdr[5]
dtb[5]
rcc[5]
hbsel
fc[13]
fhs[5]
rcf[5]
ents
fd[5]
fo[5]
fc[5]
D5
adctuneovr
lnacomp[2]
enphpwdn
cpforcedn
vcocorr[2]
Reserved
chfilval[4]
Reserved
Reserved
Reserved
Reserved
Reserved
oscdeten
txaethr[4]
chhd[28]
chhd[20]
chhd[12]
hden[28]
hden[20]
hden[12]
rxplen[4]
txmod[0]
cpcorr[4]
d3trim[0]
vcocal[4]
endv1p5
dtmod[0]
txafthr[4]
rxafthr[4]
pklen[4]
rxhd[28]
rxhd[20]
rxhd[12]
enrcfcal
chhd[4]
hden[4]
adc8[4]
txdr[12]
lnagain
firval[4]
txhd[4]
rxhd[4]
dsmod
clkhyst
enifldo
enrc32
envcm
fhch[4]
fifod[4]
pllts[1]
txdr[4]
atb[4]
dtb[4]
enbf4
rcc[4]
fc[12]
fhs[4]
enpa
rcf[4]
fd[4]
fo[4]
fb[4]
fc[4]
D4
Data
Alt_PA_Seq
lnacomp[1]
ldoramp[1]
adctune[3]
dsorder[1]
chfiladd[3]
vcocorr[1]
Reserved
Reserved
Reserved
dvbshunt
chfilval[3]
adcoloop
Reserved
txaethr[3]
hden[27]
hden[19]
cpcorr[3]
d2trim[1]
vcocal[3]
enbias2x
rxafthr[3]
chhd[27]
chhd[19]
chhd[11]
hden[11]
rxplen[3]
manppol
txafthr[3]
rxhd[27]
rxhd[19]
rxhd[11]
pklen[3]
hden[3]
cdconly
chhd[3]
adc8[3]
firval[3]
Ina_sw
txdr[11]
txhd[3]
rxhd[3]
enrfldo
fhch[3]
fifod[3]
pllts[0]
OOkth
txdr[3]
atb[3]
dtb[3]
enbf5
enbf3
rcc[3]
fhs[3]
eninv
fc[11]
rccal
rcf[3]
pga3
fd[3]
fo[3]
fb[3]
fc[3]
D3
turn_around
lnacomp[0]
ldoramp[0]
dsorder[0]
chfiladd[2]
adctune[2]
vcocorr[0]
chfilval[2]
enmaninv
Reserved
txaethr[2]
cdccur[2]
enamp2x
chhd[26]
chhd[18]
chhd[10]
hden[26]
hden[18]
hden[10]
rxplen[2]
vcocaldp
cpcorr[2]
d2trim[0]
vcocal[2]
adcref[2]
txafthr[2]
rxafthr[2]
rxhd[10]
refclksel
txpow[2]
pklen[2]
rxhd[26]
rxhd[18]
enpllldo
firadd[2]
rcosc[2]
chhd[2]
hden[2]
adc8[2]
endv32
diglvl[2]
txdr[10]
firval[2]
txhd[2]
rxhd[2]
pllt0[2]
enbf11
fhch[2]
fifod[2]
txdr[2]
envco
atb[2]
dtb[2]
rcc[2]
fc[10]
fhs[2]
rcf[2]
pga2
fd[8]
fd[2]
fo[2]
fb[2]
fc[2]
_en
D2
d1p5trim[1]
adctune[1]
chfiladd[1]
modtyp[1]
txramp[1]
dsrstmod
chfilval[1]
enmanch
txaethr[1]
hden[25]
hden[17]
cdccur[1]
vcocur[1]
vcocal[1]
Phase[1]
rxafthr[1]
chhd[25]
chhd[17]
rxplen[1]
cpcorr[1]
endigldo
adcref[1]
txpow[1]
txafthr[1]
rxhd[25]
rxhd[17]
refclkinv
pgath[1]
firadd[1]
pklen[1]
hden[9]
hden[1]
diglvl[1]
rcosc[1]
chhd[9]
chhd[1]
adc8[1]
firval[1]
txhd[1]
rxhd[9]
rxhd[1]
enbf12
fhch[1]
fifod[1]
pllt0[1]
vcocal
bufovr
txdr[9]
txdr[1]
atb[1]
dtb[1]
enbf2
rcc[1]
fhs[1]
encp
rcf[1]
pga1
fd[1]
fo[1]
fo[9]
fb[1]
fc[1]
fc[9]
D1
d1p5trim[0]
endigpwdn
adctune[0]
chfiladd[0]
modtyp[0]
txramp[0]
pa_vbias_
chfilval[0]
txaethr[0]
cdccur[0]
vcocur[0]
vcocal[0]
Phase[0]
rxafthr[0]
chhd[24]
chhd[16]
hden[24]
hden[16]
rxplen[0]
cpcorr[0]
adcref[0]
txafthr[0]
rxhd[24]
rxhd[16]
pgath[0]
firadd[0]
txpow[0]
pklen[0]
diglvl[0]
enwhite
rcosc[0]
chhd[8]
chhd[0]
hden[8]
hden[0]
adc8[0]
skipvco
distogg
pllreset
firval[0]
rxhd[8]
rxhd[0]
enmx2
txhd[0]
pllt0[0]
fhch[0]
fifod[0]
txdr[8]
txdr[0]
atb[0]
dtb[0]
enbuf
rcc[0]
fhs[0]
boost
dsrst
enbg
rcf[0]
pga0
fd[0]
fo[0]
fo[8]
fb[0]
fc[8]
fc[0]
D0
Default
POR
FFh
FFh
FFh
FFh
2Fh
0Eh
1Dh
1Dh
0Ah
3Dh
0Ch
BBh
00h
00h
00h
00h
00h
00h
00h
00h
00h
52h
14h
44h
00h
00h
80h
40h
03h
00h
00h
40h
00h
00h
00h
24h
00h
00h
81h
02h
03h
20h
00h
01h
08h
00h
20h
00h
00h
75h
80h
09h
00h
00h
09h
37h
04h
37h
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