SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 154

• Manufacturer Part Number: SI4431-A0-FM
• Description: IC TXRX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-A0-FM

• Package / Case: 20-QFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 28 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1633-5

Register 7Dh. TX FIFO Control 2
Register 7Eh. RX FIFO Control
Register 7Fh. FIFO Access
Si4431
Reset value = 00000100
Reset value = 00110111
Reset value = NA
154
Name
Name
Name
Type
Type
Type
Bit
Bit
Bit
7:6
5:0
7:6
5:0
7:0
Bit
Bit
Bit
txfaethr[5:0]
rxafthr[5:0]
Reserved
Reserved
fifod[7:0]
Name
Name
Name
D7
D7
D7
Reserved
Reserved
R/W
R/W
Reserved.
TX FIFO Almost Empty Threshold.
Reserved.
RX FIFO Almost Full Threshold.
FIFO Data.
A Write (R/W = 1) to this Address will begin a Burst Write to the TX FIFO. The FIFO will
be loaded in the same manner as a Burst SPI Write but the SPI address will not be incre-
mented. To conclude the TX FIFO Write the SEL pin should be brought HIGH. A Read
(R/W = 0) to this address will begin a burst read of the RX FIFO, in the same manner.
D6
D6
D6
D5
D5
D5
Preliminary Rev. 0.4
D4
D4
D4
fifod[7:0]
R/W
Function
Function
Function
D3
D3
D3
txfaethr[5:0]
rxafthr[5:0]
R/W
R/W
D2
D2
D2
D1
D1
D1
D0
D0
D0