SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 87

• Manufacturer Part Number: SI4431-A0-FM
• Description: IC TXRX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-A0-FM

• Package / Case: 20-QFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 28 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1633-5

Register 04h. Interrupt/Status 2
Reset value = xxxxxxxx
When any of the Interrupt/Status Register 2 bits change state from 0 to 1 the control block will notify the
microcontroller by setting the nIRQ pin LOW if it is enabled in the Interrupt Enable 2 register. The nIRQ pin will go
to HIGH and all the enabled interrupt bits will be cleared when the microcontroller reads this address. If any of
these bits is not enabled in the Interrupt Enable 2 register then it becomes a status signal that can be read anytime
in the same location and will not be cleared by reading the register.
Name
Type
Bit
Bit
7
6
5
4
3
2
1
0
ipreainval
iswdet
ipreaval
ichiprdy
Name
iswdet
D7
R
irssi
iwut
ipor
ilbd
ipreaval
Sync Word Detected.
When a sync word is detected this bit will be set to 1.
Valid Preamble Detected.
When a preamble is detected this bit will be set to 1.
Invalid Preamble Detected.
When the preamble is not found within a period of time set by the invalid preamble detec-
tion threshold in Register 54h, this bit will be set to 1.
RSSI.
When RSSI level exceeds the programmed threshold this bit will be set to 1.
Wake-Up-Timer.
On the expiration of programmed wake-up timer this bit will be set to 1.
Low Battery Detect.
When a low battery event is been detected this bit will be set to 1. This interrupt event is
saved even if it is not enabled by the mask register bit and causes an interrupt after it is
enabled.
Chip Ready (XTAL).
When a chip ready event has been detected this bit will be set to 1.
Power-on-Reset (POR).
When the chip detects a Power on Reset above the desired setting this bit will be set to 1.
D6
R
ipreainval
D5
R
Preliminary Rev. 0.4
irssi
D4
R
Function
iwut
D3
R
ilbd
D2
R
ichiprdy
D1
R
Si4431
ipor
D0
R
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