SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 134
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SI4431-A0-FM
Manufacturer Part Number
SI4431-A0-FM
Description
IC TXRX ISM 930MHZ 3.6V 20-QFN
Manufacturer
Silicon Laboratories Inc
Specifications of SI4431-A0-FM
Package / Case
20-QFN
Mfg Application Notes
Transitioning SI4430/31 to Rev B
Frequency
240MHz ~ 930MHz
Data Rate - Maximum
128kbps
Modulation Or Protocol
FSK, GFSK, OOK
Power - Output
13dBm
Sensitivity
-118dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
18.5mA
Current - Transmitting
28mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Number Of Receivers
2
Number Of Transmitters
1
Wireless Frequency
240 MHz to 930 MHz
Output Power
13 dBm
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
28 mA
Minimum Operating Temperature
- 40 C
Modulation
FSK, GFSK, OOK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1633-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI4431-A0-FMR
Manufacturer:
SILICON
Quantity:
3 500
Part Number:
SI4431-A0-FMR
Manufacturer:
SILICONLABS/芯科
Quantity:
20 000
Register 56h. Modem Test
Register 57h. Charge Pump Test
Si4431
Reset value = 00000000
Reset value = 00000000
134
Name
Name
Type
Type
Bit
Bit
2:0
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
cdcurr[2:0]
cpforceup
cpforcedn
bcrfbyp
oscdeten
fbdiv_rst
refclksel
refclkinv
pfdrst
cdconly
bcrfbyp
slicfbyp
distogg
R/W
R/W
Name
Name
dttype
D7
D7
pfdrst
ookth
fbdiv_rst
slicfbyp
If set, BCR phase compensation will be bypassed.
If set, slicer phase compensation will be bypassed.
Dithering Type.
If low and dither enabled, we add +1/0, otherwise if high and dithering enabled, we add
±1.
If low, the ADC Oscillation Detection mechanism is allowed to work. If set, we disable the
function.
If set, in OOK mode, the slicer threshold will be estimated by 8 bits of preamble. By
default, this bit is low and the demod estimate the threshold after 4 bits.
Delta-Sigma Reference Clock Source Selection
1:
0:
Delta-Sigma Reference Clock Inversion Enable.
If reset, the discriminator toggling is disabled.
Direct Control to Analog.
Direct Control to Analog.
Charge Pump Force Up.
Charge Pump Force Down.
Charge Pump DC Offset Only.
Charge Pump DC Current Selection.
R/W
R/W
D6
D6
10 MHz
PLL
cpforceup
dttype
R/W
R/W
D5
D5
Preliminary Rev. 0.4
cpforcedn
oscdeten
R/W
R/W
D4
D4
Function
Function
cdonly
ookth
R/W
R/W
D3
D3
refclksel
R/W
D2
D2
cdcurr[2:0]
refclkinv
R/W
R/W
D1
D1
distogg
R/W
D0
D0