SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 46

• Manufacturer Part Number: SI4431-A0-FM
• Description: IC TXRX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-A0-FM

• Package / Case: 20-QFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 28 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1633-5

Si4431
46
Add
3C
3D
30
31
32
33
34
35
36
37
38
39
3A
3B
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
Preamble Detection Control
Function/Description
Received Packet Length
Transmit Packet Length
Data Access Control
Received Header 3
Received Header 2
Received Header 1
Received Header 0
Transmit Header 3
Transmit Header 2
Transmit Header 1
Transmit Header 0
Header Control 1
Header Control 2
Preamble Length
Header Enable 3
Header Enable 2
Header Enable 1
Header Enable 0
Check Header 3
Check Header 2
Check Header 1
Check Header 0
EzMAC status
Sync Word 3
Sync Word 2
Sync Word 1
Sync Word 0
prealen[7]
Reserved
preath[4]
chhd[31]
chhd[23]
chhd[15]
hden[31]
hden[23]
hden[15]
rxplen[7]
sync[31]
sync[23]
sync[15]
enpacrx
txhd[31]
txhd[23]
txhd[15]
pklen[7]
rxhd[31]
rxhd[23]
rxhd[15]
bcen[3]
chhd[7]
hden[7]
sync[7]
txhd[7]
rxhd[7]
D7
0
Table 14. Packet Handler Registers
enbcast[2]
prealen[6]
preath[3]
hden[30]
hden[22]
hden[14]
sync[30]
sync[22]
sync[14]
chhd[30]
chhd[22]
chhd[14]
rxplen[6]
hdlen[2]
txhd[30]
txhd[22]
txhd[14]
rxhd[30]
rxhd[22]
rxhd[14]
pklen[6]
hden[6]
sync[6]
chhd[6]
txhd[6]
rxhd[6]
lsbfrst
rxcrc1
D6
Preliminary Rev. 0.4
enbcast[1]
prealen[5]
preath[2]
hden[29]
hden[21]
hden[13]
rxplen[5]
crcdonly
sync[29]
sync[21]
sync[13]
chhd[29]
chhd[21]
chhd[13]
hdlen[1]
txhd[29]
txhd[21]
txhd[13]
pklen[5]
rxhd[29]
rxhd[21]
rxhd[13]
hden[5]
sync[5]
chhd[5]
pksrch
txhd[5]
rxhd[5]
D5
enbcast[0]
prealen[4]
preath[1]
chhd[28]
chhd[20]
chhd[12]
hden[28]
hden[20]
hden[12]
rxplen[4]
sync[28]
sync[20]
sync[12]
rxhd[28]
rxhd[20]
rxhd[12]
hdlen[0]
txhd[28]
txhd[20]
txhd[12]
pklen[4]
chhd[4]
hden[4]
sync[4]
txhd[4]
rxhd[4]
pkrx
D4
*
prealen[3]
preath[0]
chhd[27]
chhd[19]
chhd[11]
hden[27]
hden[19]
hden[11]
rxplen[3]
sync[27]
sync[19]
sync[11]
rxhd[27]
rxhd[19]
enpactx
txhd[27]
txhd[19]
txhd[11]
pklen[3]
rxhd[11]
hdch[3]
fixpklen
chhd[3]
hden[3]
pkvalid
sync[3]
rxhd[3]
txhd[3]
D3
synclen[1]
prealen[2]
Reserved
hden[26]
hden[18]
hden[10]
sync[26]
sync[18]
sync[10]
chhd[26]
chhd[18]
chhd[10]
rxplen[2]
txhd[26]
txhd[18]
txhd[10]
rxhd[26]
rxhd[18]
rxhd[10]
crcerror
pklen[2]
hdch[2]
chhd[2]
hden[2]
sync[2]
txhd[2]
rxhd[2]
encrc
D2
synclen[0]
prealen[1]
Reserved
hden[25]
hden[17]
sync[25]
sync[17]
chhd[25]
chhd[17]
rxplen[1]
txhd[25]
txhd[17]
rxhd[25]
rxhd[17]
pklen[1]
hden[9]
hden[1]
hdch[1]
sync[9]
sync[1]
chhd[9]
chhd[1]
txhd[9]
txhd[1]
rxhd[9]
rxhd[1]
crc[1]
pktx
D1
prealen[8]
prealen[0]
Reserved
chhd[24]
chhd[16]
hden[24]
hden[16]
rxplen[0]
sync[24]
sync[16]
rxhd[24]
rxhd[16]
txhd[24]
txhd[16]
pklen[0]
hdch[0]
chhd[8]
chhd[0]
hden[8]
hden[0]
sync[8]
sync[0]
rxhd[8]
rxhd[0]
pksent
txhd[8]
txhd[0]
crc[0]
D0
POR Def.
1Dh
0Ch
2Dh
D4h
FFh
22h
07h
20h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
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