IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 10

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

1–4
Table 1–3. DDR3 SDRAM HPC and HPC II Features (Part 1 of 2)
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Half-rate controller
Support for AFI ALTMEMPHY
Support for Avalon
Support for Native local interface
Configurable command look-ahead bank management with in-order reads and
writes
Additive latency
Optional support for multi-cast write for t
Support for arbitrary Avalon burst length
Built-in flexible memory burst adapter
Configurable Local-to-Memory address mappings
Integrated half-rate bridge for low latency option
Optional run-time configuration of size and mode register settings, and memory
timing
Partial array self-refresh (PASR)
Support for industry-standard DDR3 SDRAM devices; and DIMMs
Optional support for self-refresh command
Optional support for user-controlled power-down command
Optional support for automatic power-down command with programmable
time-out
Optional support for auto-precharge read and auto-precharge write commands
Optional support for user-controller refresh
Reduced bank tracking for area optimization
Controller variable latency
Optional multiple controller clock sharing in SOPC Builder Flow
Integrated error correction coding (ECC) function 72-bit
Integrated ECC function 40-bit
Support for partial-word write with optional automatic error correction
SOPC Builder ready
Support for OpenCore Plus evaluation
®
Memory Mapped (Avalon-MM) local interface
■
■
In addition,
HPC II.
No support for data-mask (DM) pins for ×4 DDR3 SDRAM DIMMs or
components, so select No for Drive DM pins from FPGA when using ×4 devices.
The ALTMEMPHY megafunction supports half-rate DDR3 SDRAM interfaces
only.
Features
Table 1–3
RC
mitigation
shows the features provided by the DDR3 SDRAM HPC and
HPC
Controller Architecture
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December 2010 Altera Corporation
Chapter 1: About This IP
HPC II
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Features