IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 56

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–4
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Figure 5–2
Figure 5–2. Calibration Flow—Without Leveling
Step 1: Memory Device Initialization
This step initializes the memory device according to the DDR3 SDRAM specification.
The initialization procedure includes resetting the memory device, specifying the
mode registers and memory device ODT setting, and initializing the memory device
DLL. Calibration requires overriding some of the user-specified mode register
settings, which are reverted in
Step 2: Write Training Patterns
In this step, a pattern is written to the memory to be read in later calibration stages.
The matched trace lengths to DDR3 SDRAM devices mean that after memory
initialization, write capture functions. The pattern is 0x30F5 and comprises the
following separately written patterns:
■
■
■
All 0: ‘b0000 - DDIO high and low bits held at 0
All 1: ‘b1111 - DDIO high and low bits held at 1
Toggle: ‘b0101 - DDIO high bits held at 0 and DDIO low bits held at 1
shows the calibration flow.
VT Tracking
“Step 7: Prepare for User
Read Resynchronization
Address and Command
Prepare for User Mode
and PHY Initialization
Chapter 5: Functional Description—ALTMEMPHY
Datapath Timing
Memory Device
Read and Write
Write Training
Clock Phase
Clock Cycle
User Mode
Postamble
Patterns
Mode”.
December 2010 Altera Corporation
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