IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 133

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Functional Description—High-Performance Controller II
Top-level Signals Description
Table 7–6. CSR Interface Signals (Part 2 of 2) (Part 2 of 2)
Table 7–7. DDR3 SDRAM Interface Signals
December 2010 Altera Corporation
csr_rdata_valid
csr_waitrequest
mem_dq[]
mem_dqs[]
mem_dqs_n[]
mem_clk
mem_clk_n
mem_addr[]
mem_ac_parity
mem_ba[]
mem_cas_n
mem_cke[]
mem_cs_n[]
mem_dm[]
mem_odt
mem_ras_n
mem_we_n
parity_error_n
mem_err_out_n
Notes to
(1) The mem_clk signals are output only signals from the FPGA. However, in the Quartus II software they must be defined as bidirectional (INOUT)
(2) This signal is for Registered DIMMs only.
I/Os to support the mimic path structure that the ALTMEMPHY megafunction uses.
Signal Name
Table
Signal Name
(1)
(1)
7–7:
(2)
(2)
(2)
Table 7–7
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Direction
shows the DDR3 SDRAM HPC II interface signals.
Output
Output
Memory data bus. This bus is half the width of the local read and write data
busses.
Memory data strobe signal, which writes data into the DDR3 SDRAM and
captures read data into the Altera device.
Inverted memory data strobe signal, which is used together with the mem_dqs
signal to improve signal integrity.
Clock for the memory device.
Inverted clock for the memory device.
Memory address bus.
Address or command parity signal generated by the PHY and sent to the
DIMM.
Memory bank address bus.
Memory column address strobe signal.
Memory clock enable signals.
Memory chip select signals.
Memory data mask signal, which masks individual bytes during writes.
Memory on-die termination control signal.
Memory row address strobe signal.
Memory write enable signal.
Active-low signal that is asserted when a parity error occurs and stays
asserted until the PHY is reset.
Signal sent from the DIMM to the PHY to indicate that a parity error has
occured for a particular cycle.
Read data valid signal. The csr_rdata_valid signal indicates that valid data
is present on the read data bus.
The csr_waitrequest signal indicates that the HPC II is busy and not ready
to accept request signals. If the csr_waitrequest signal goes high in the
clock cycle when a read or write request is asserted, that request is not
accepted. If the csr_waitrequest signal goes low, the HPC II is then ready
to accept more requests.
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Description
Description
External Memory Interface Handbook Volume 3
7–17