IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 104

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–10
Table 6–4. ECC Registers (Part 1 of 3)
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Control word specifications
Maximum single-bit error
counter threshold
Maximum double-bit error
counter threshold
Current single-bit error
count
Current double-bit error
count
Last or first single-bit error
error address
Name
Table 6–3
Table 6–3. Burst Lengths and Rates
Local Burst Length 2
For a local burst length of 2, the write latency increases by two clock cycles; the read
latency increases by one clock cycle (including checking and correction).
A partial write results in a read followed by write in the ECC logic, so latency
depends on the time the controller takes to fetch the data from the particular address.
For a single-bit error, the automatic correction of memory takes place without stalling
the read cycle (if enabled), which stalls further commands to the ECC logic, while the
correction takes place.
ECC Registers
Table 6–4
Local Burst Length
Address
00
01
02
03
04
05
shows the relationship between burst lengths and rate.
shows the ECC registers.
1
2
(Bits)
Size
32
32
32
32
32
32
Attribute
R/W
R/W
R/W
RO
RO
RO
Chapter 6: Functional Description—High-Performance Controller
00000001
00000001
00000000
00000000
00000000
0000000F
Default
Rate
Half
Full
This register contains all commands for
the ECC functioning.
The single-bit error counter increments
(when a single-bit error occurs) until the
maximum threshold, as defined by this
register. When this threshold is crossed,
the ECC logic generates an interrupt.
The double-bit error counter increments
(when a double-bit error occurs) until the
maximum threshold, as defined by this
register. When this threshold is crossed,
the ECC logic generates an interrupt.
The single-bit error counter increments
(when a single-bit error occurs) until the
maximum threshold. You can find the
value of the count by reading this status
register.
The double-bit error counter increments
(when a double-bit error occurs) until the
maximum threshold. You can find the
value of the count by reading this status
register.
This status register stores the last
single-bit error error address. It can be
cleared using the control word clear. If bit
10 of the control word is set high, the
first occurred address is stored.
December 2010 Altera Corporation
Memory Burst Length
Description
4
4
Block Description