IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 167
![IP CORE Renewal Of IP-HPMCII](/photos/24/19/241941/4696148_sml.jpg)
IPR-HPMCII
Manufacturer Part Number
IPR-HPMCII
Description
IP CORE Renewal Of IP-HPMCII
Manufacturer
Altera
Datasheet
1.IP-HPMCII.pdf
(176 pages)
Specifications of IPR-HPMCII
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Arria II GX, HardCopy III, Stratix III, Stratix IV
Core Architecture
FPGA
Core Sub-architecture
Arria, HardCopy, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers II
December 2010 Altera Corporation
The following sequence corresponds with the numbered items in
1. The user logic asserts the first local_write_req signal with a size of 2 and an
2. The user logic asserts the second local_write_req signal with a size of 2 and an
3. The controller issues the necessary memory command and address signals to the
4. The controller asserts the afi_wdata_valid signal to indicate to the ALTMEMPHY
5. The controller asserts the afi_dqs_burst signals to control the timing of the DQS
6. The ALTMEMPHY megafunction issues the write command, and sends the write
7. The controller generates another write because the first write is to a non-aligned
address of 0×000001. The local_ready signal is asserted along with the
local_write_req signal, which indicates that the controller has accepted this
request, and the user logic can request another read or write in the following clock
cycle. If the local_ready signal was not asserted, the user logic must keep the
write request, size, and address signals asserted until the local_ready signal is
registered high. The local address 0x000001 is mapped to the following memory
address in half-rate mode:
mem_row_address = 0×0000
mem_col_address = 0×000001<<2 = 0×000004
mem_bank_address = 0×00
address of 0×000003. The local address 0×000003 is mapped to the following
memory address in half-rate mode:
mem_row_address = 0×0000
mem_col_address = 0×000003<<2 = 0×00000C
mem_bank_address = 0×00
ALTMEMPHY megafunction for it to send to the memory device.
megafunction that valid write data and write data masks are present on the inputs
to the ALTMEMPHY megafunction.
signal that the ALTMEMPHY megafunction issues to the memory.
data and write DQS to the memory.
memory address, 0×0004. The controller performs the second write burst at the
memory address of 0×0008.
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
Figure
9–11:
9–21
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