IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 25

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Generated Files
Table 2–5. Controller Generated Files—DDR3 High-Performance Controller (HPC)
.
Table 2–6. Controller Generated Files—DDR3 High-Performance Controller II (HPC II)
December 2010 Altera Corporation
<variation name>_auk_ddr_hp_controller_wrapper.vo
or .vho
<variation_name>_auk_ddr_hp_controller_ecc_
wrapper.vo or .vho
<variation name>_alt_ddrx_controller_wrapper.v or .vho
alt_ddrx_addr_cmd.v
alt_ddrx_afi_block.v
alt_ddrx_bank_tracking.v
alt_ddrx_clock_and_reset.v
alt_ddrx_cmd_queue.v
alt_ddrx_controller.v
alt_ddrx_csr.v
alt_ddrx_ddr3_odt_gen.v
alt_ddrx_avalon_if.v
alt_ddrx_decoder_40.v
alt_ddrx_decoder_72.v
alt_ddrx_decoder.v
alt_ddrx_encoder_40.v
alt_ddrx_encoder_72.v
alt_ddrx_encoder.v
alt_ddrx_input_if.v
alt_ddrx_odt_gen.v
alt_ddrx_state_machine.v
alt_ddrx_timers_fsm.v
alt_ddrx_timers.v
alt_ddrx_wdata_fifo.v
alt_avalon_half_rate_bridge_constraints.sdc
alt_avalon_half_rate_bridge.v
Filename
Filename
VHDL or Verilog HDL IP functional simulation model.
ECC functional simulation model.
A controller wrapper that instantiates the alt_ddrx_controller.v
file and configures the controller accordingly by the wizard.
Decodes the state machine outputs into the memory address
and command signals.
Generates the read and write control signals for the AFI.
Tracks which row is open in which memory bank.
Contains the clock and reset logic.
Contains the command queue logic.
The controller top-level file that instantiates all the sub-blocks.
Contains the control and status register interface logic.
Generates the on-die termination (ODT) control signal for
DDR3 memory interfaces.
Communicates with the Avalon-MM interface.
Contains the 40 bit version of the ECC decoder logic.
Contains the 72 bit version of the ECC decoder logic.
Instantiates the appropriate width ECC decoder logic.
Contains the 40 bit version of the ECC encoder logic.
Contains the 72 bit version of the ECC encoder logic.
Instantiates the appropriate width ECC encoder logic.
The input input interface block. It instantiates the
alt_ddrx_cmd_queue.v, alt_ddrx_wdata_fifo.v, and
alt_ddrx_avalon_if.v files.
Instantiates the alt_ddrx_ddr3_odt_gen.v file selectively. It
also controls the ODT addressing scheme.
The main state machine of the controller.
The state machine that tracks the per-bank timing parameters.
Instantiates alt_ddrx_timers_fsm.v and contains the rank
specific timing tracking logic.
The write data FIFO logic. This logic buffers the write data and
byte enables from the Avalon interface.
Contains timing constraints if your design has the Enable Half
Rate Bridge option turned on.
The integrated half-rate bridge logic block.
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
Description
Description
2–9