IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 19

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
SOPC Builder Flow
December 2010 Altera Corporation
Completing the SOPC Builder System
6. Click Finish to complete parameterizing the DDR3 SDRAM Controller with
To complete the SOPC Builder system, perform the following steps:
1. In the System Contents tab, select Nios II Processor and click Add.
2. On the Nios II Processor page, in the Core Nios II tab, select altmemddr for Reset
3. Change the Reset Vector Offset and the Exception Vector Offset to an Avalon
Table 2–1. Avalon-MM Addresses for AFI Mode
4. Click Finish.
5. On the System Contents tab, expand Interface Protocols and expand Serial.
6. Select JTAG UART and click Add.
7. Click Finish.
ALTMEMPHY IP and add it to the system.
Vector and Exception Vector.
address that is not written to by the ALTMEMPHY megafunction during its
calibration process.
c
To calculate the Avalon-MM address equivalent of the memory address range 0×0
to 0×47, multiply the memory address by the width of the memory interface data
bus in bytes. Refer to
1
External Memory Interface
The ALTMEMPHY megafunction performs memory interface calibration
every time it is reset, and in doing so, writes to a range of addresses. If you
want your memory contents to remain intact through a system reset, you
should avoid using these memory addresses. This step is not necessary if
you reload your SDRAM memory contents from flash every time you reset
your system.
If you are upgrading your Nios system design from version 8.1 or previous,
ensure that you change the Reset Vector Offset and the Exception Vector
Offset to AFI mode.
If there are warnings about overlapping addresses, on the System menu,
click Auto Assign Base Addresses.
If you enable ECC and there are warnings about overlapping IRQs, on the
System menu click Auto Assign IRQs.
Width
16
32
64
8
Table 2–1
for more Avalon-MM addresses.
Reset Vector Offset
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
0
0
0
0
× 120
× 240
× 60
× A0
External Memory Interface Handbook Volume 3
Exception Vector Offset
0
0
0
0
× 140
× 260
× 80
× C0
2–3