IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 7

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

December 2010 Altera Corporation
1
The Altera
interfaces to industry-standard DDR3 SDRAM. The ALTMEMPHY megafunction is
an interface between a memory controller and the memory devices, and performs
read and write operations to the memory. The DDR3 SDRAM Controller with
ALTMEMPHY IP works in conjunction with the Altera ALTMEMPHY megafunction.
The DDR3 SDRAM Controller with ALTMEMPHY IP and ALTMEMPHY
megafunction support DDR3 SDRAM interfaces in half-rate mode. The DDR3
SDRAM Controller with ALTMEMPHY IP offers two controller architectures: the
high-performance controller (HPC) and the high-performance controller II (HPC II).
HPC II provides higher efficiency and more advanced features.
DDR3 SDRAM high-performance controller denotes both HPC and HPC II unless
indicated otherwise.
Figure 1–1 on page 1–1
file that the DDR3 SDRAM Controller with ALTMEMPHY IP creates for you.
Figure 1–1. System-Level Diagram
Note to
(1) When you choose Instantiate DLL Externally, delay-locked loop (DLL) is instantiated outside the ALTMEMPHY
The MegaWizard
an example driver, and your DDR3 SDRAM high-performance controller custom
variation. The controller instantiates an instance of the ALTMEMPHY megafunction
which in turn instantiates a phase-locked loop (PLL) and DLL. You can also
instantiate the DLL outside the ALTMEMPHY megafunction to share the DLL
between multiple instances of the ALTMEMPHY megafunction. You cannot share a
PLL between multiple instances of the ALTMEMPHY megafunction, but you may
share some of the PLL clock outputs between these multiple instances.
The example top-level file is a fully-functional design that you can simulate,
synthesize, and use in hardware. The example driver is a self-test module that issues
read and write commands to the controller and checks the read data to produce the
pass or fail, and test complete signals.
megafunction.
Figure
External
Memory
Device
®
1–1:
DDR3 SDRAM Controller with ALTMEMPHY IP provides simplified
™
Plug-In Manager generates an example top-level file, consisting of
shows a system-level diagram including the example top-level
ALTMEMPHY
DLL
PLL
(1)
Example Top-Level File
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Performance
Controller
High-
External Memory Interface Handbook Volume 3
Example
Driver
1. About This IP
Pass or Fail