IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 64

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–12
Figure 5–6. Arria II GX Address and Command Datapath
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
PHY Command Outputs
mem_cas_n
mem_ras_n
mem_we_n
mem_cs_n
mem_addr
Command
ac_clk_2x
mem_ba
mem_dq
mem-dqs
1
1
0000
00
NOP
Figure 5–6
the command in the memory device. All commands are masked when the chip-select
signal is inactive. The mem_cs_n signal is considered part of the command code.
The command interface is made up of the signals mem_ras_n, mem_cas_n, mem_we_n,
mem_cs_n, mem_cke, and mem_odt.
The waveform in
write commands. The following sequence corresponds with the numbered items in
Figure
1. The commands are asserted either on the rising edge of ac_clk_2x. The ac_clk_2x
2. All address and command signals (except for mem_cs_ns, mem_cke, and mem_odt
3. The mem_cs_n, mem_cke, and mem_odt signals are asserted during the second cycle
4. The address is incremented every other ac_clk_2x cycle.
The ac_clk_2x clock is derived from either mem_clk_2x (when you choose 0° or 180°
phase shift) or write_clk_2x (when you choose 90° or 270° phase shift).
The address and command clock can be 0, 90, 180, or 270° from the system clock.
is derived from either mem_clk_2x (0 ° ), write_clk_2x (270 ° ), or the inverted
variations of those two clocks (for 180 ° and 90 ° phase shifts). This depends on the
setting of the address and command clock in the ALTMEMPHY parameter editor.
Refer to
clock in relation to the mem_clk_2x or write_clk_2x signals.
signals) remain asserted on the bus for two clock cycles, allowing sufficient time
for the signals to settle.
of the address/command phase. By asserting the chip-select signal in alternative
cycles, back-to-back read or write commands can be issued.
5–6.
shows a 1T chip select signal (mem_cs_n), which is active low, and disables
“Address and Command Datapath” on page 5–11
Figure 5–6
PCH
NOP
[1]
shows a NOP command followed by five back-to-back
[1]
0001
ACT
[2]
0000
NOP
[3]
WR
[3]
[4]
0004
Chapter 5: Functional Description—ALTMEMPHY
[4]
0008
[4]
000C
December 2010 Altera Corporation
for illustrations of this
0010
0000
NOP
Block Description