IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 145

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 8: Latency
December 2010 Altera Corporation
f
1
You can separate the controller and ALTMEMPHY read data input latency into
latency that occurred in the I/O element (IOE) and latency that occurred in the FPGA
fabric.
Table 8–2
definitions for half rate controller for Stratix III and Stratix IV devices.
The exact latency depends on your precise configuration. You should obtain precise
latency from simulation, but this figure may vary in hardware because of the
automatic calibration process.
Table 8–2. Typical Latency
To see the latency incurred in the IOE for both read and write paths for ALTMEMPHY
variations in Stratix IV and Stratix III devices refer to the IOE figures in the
Memory Interfaces in Stratix III Devices
External Memory Interfaces in Stratix IV Devices
Handbook.
Stratix III
Stratix IV
Device
shows the read and write latency derived from the write and read latency
Controller
Rate
Half
Half
Frequency
(MHz)
400
400
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
chapter of the Stratix III Device Handbook and the
Latency
chapter of the Stratix IV Device
Write
Write
Read
Read
Type
External Memory Interface Handbook Volume 3
Local Clock
Cycles
23
14
23
14
Total Latency
External
Time
(ns)
115
115
68
68
8–3