IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 147

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

DDR3 High-Performance Controllers
December 2010 Altera Corporation
This chapter details the timing diagrams for the DDR3 SDRAM high-performance
controllers (HPC) and high-performance controllers II (HPC II).
This section discusses the following timing diagrams for HPC in AFI mode:
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“Auto-Precharge”
“User Refresh”
“Half-Rate Read for Avalon Interface”
“Half-Rate Write for Avalon Interface”
“Half Rate Write for Native Interface”
“Initialization Timing for HPC”
“Calibration Timing for HPC”
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
9. Timing Diagrams