IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 54

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–2
Block Description
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Figure 5–1 on page 5–2
and how it interfaces with the external memory device and the controller. The
ALTPLL megafunction is instantiated inside the ALTMEMPHY megafunction, so that
you do not need to generate the clock to any of the ALTMEMPHY blocks.
Figure 5–1. ALTMEMPHY Megafunction Interfacing with the Controller and the External Memory
The ALTMEMPHY megafunction comprises the following blocks:
■
■
■
■
■
Write datapath
Address and command datapath
Clock and reset management, including DLL and PLL
Sequencer for calibration
Read datapath
External
Memory
Device
shows the major blocks of the ALTMEMPHY megafunction
FPGA
ALTMEMPHY
Command
Sequencer
Datapath
Management
Datapath
Address
Datapath
Write
and Reset
Read
and
Clock
DLL
PLL
Controller
Memory
Chapter 5: Functional Description—ALTMEMPHY
December 2010 Altera Corporation
Logic
User
Block Description