IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 61

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—ALTMEMPHY
Block Description
December 2010 Altera Corporation
Figure 5–5
Figure 5–5. Calibration Flow—DDR3 SDRAM (with leveling)
Step 1: Memory Device Initialization
This step initializes the memory device per the DDR3 SDRAM specification. The
initialization procedure includes resetting the memory device, specifying the mode
registers and memory device ODT setting, and initializing the memory device DLL.
Some of these settings may be different to those you set; however, these are changed
to the correct values (at the end of calibration) in
shows the calibration flow.
VT Tracking
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Read Resynchronization
Address and Command
Prepare for User Mode
and PHY Initialization
“Step 8: Prepare for User
Datapath Timing
Memory Device
Read and Write
Write Leveling
Write Training
Clock Phase
Clock Cycle
Write Clock
Path Setup
Postamble
User Mode
External Memory Interface Handbook Volume 3
Patterns
Mode”.
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