IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 120

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–4
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Write Data FIFO Buffer
Command Queue
Bank Management Logic
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For every Avalon transaction, the number of read or write requests cannot exceed the
the maximum local burst count of 64. Altera recommends that you set this maximum
burst count to match your system master's supported burst count.
The write data FIFO buffer holds the write data and byte-enable from the user logic
until the main state machine requests for the data. The local_ready signal is
deasserted when either the command queue or write data FIFO buffer is full. The
write data FIFO buffer is wide enough to store the write data and the byte-enable
signals.
The command queue allows the controller to buffer up to eight consecutive reads or
writes. The command queue presents the next 4, 6, or 8 accesses to the internal logic
for the look-ahead bank management. The bank management is more efficient if the
look-ahead is deeper, but a deeper queue consumes more resources, and may cause
maximum frequency degradation.
In addition to storing incoming commands, the command queue also maps the local
address to memory address based on the address mapping option selected. By
default, the command queue leverages the bank interleaving scheme, where the
address increment goes to the next bank instead of the next row to increase chances of
page hit.
The bank management logic keeps track of the current state in each bank across
multiple chips. It can keep a row open in every bank in your memory system. When a
command is issued by the state machine, the bank management logic is updated with
the latest bank status. The main state machine uses its look-ahead capability to issue
early bank management commands. The controller supports a close-page policy,
where a bank is closed after it is used.
The bank management logic also includes a reduced bank tracking feature that
reduces the controller's resource usage. This feature allows you to reduce the number
of bank tracking blocks in the bank management logic. However, the number of bank
tracking blocks used is limited because the controller is limited to the number of
pages it keeps open at any given time. This limit is determined by the controller’s
command queue look-ahead depth.
The reduced bank tracking feature provides the ability for the controller to
dynamically allocate a memory bank to be tracked to one of the available bank
tracking block. When you do not need the memory bank to be tracked anymore, the
memory bank is no longer allocated.
This feature is useful if your design is highly dependent on the total number of banks.
Using this feature may have an impact on the memory bus efficiency, but it allows a
trade-off between area and efficiency. The higher the number of banks to track, the
better the efficiency.
For single chip select:
width = row bits + bank bits + column – 2
Chapter 7: Functional Description—High-Performance Controller II
December 2010 Altera Corporation
Block Description