IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 163

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers II
December 2010 Altera Corporation
The following sequence corresponds with the numbered items in
1. The user logic asserts the first write request to row 0 so that row 0 is open before
2. The user logic asserts a second local_write_req signal with size of 2 and address
3. The controller issues the necessary memory command and address signals to the
4. The controller asserts the afi_wdata_valid signal to indicate to the ALTMEMPHY
5. The controller asserts the afi_dqs_burst signals to control the timing of the DQS
6. The ALTMEMPHY megafunction issues the write command, and sends the write
the next transaction.
of 0 (col = 0, row = 0, bank = 0, chip = 0). The local_ready signal is asserted along
with the local_write_req signal, which indicates that the controller has accepted
this request, and the user logic can request another read or write in the following
clock cycle. If the local_ready signal was not asserted, the user logic must keep
the write request, size, and address signals asserted until the local_ready signal is
registered high.
ALTMEMPHY megafunction for it to send to the memory device.
megafunction that valid write data and write data masks are present on the inputs
to the ALTMEMPHY megafunction.
signal that the ALTMEMPHY megafunction issues to the memory.
data and write DQS to the memory.
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
Figure
9–9:
9–17