IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 137

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Functional Description—High-Performance Controller II
Register Maps Description
Table 7–12. Address 0x100 ALTMEMPHY Status and Control Register
Table 7–13. Address 0x110 Controller Status and Configuration Register (Part 1 of 2)
December 2010 Altera Corporation
30:14
13:8
15:0
Bit
7:3
Bit
16
0
1
2
Controller Register Map
CAL_SUCCESS
CAL_FAIL
CAL_REQ
Reserved
CLOCK_OFF
Reserved
AUTO_PD_CYCLES
AUTO_PD_ACK
Name
Name
The controller register map allows you to control the memory controller settings. To
access the controller register map, connect the CSR interface signals in
the Avalon-MM protocol.
Default
—
—
0
0
0
0
Default
0x0
1
Access
RW
RW
RO
RO
—
—
Access
RW
RO
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
This bit reports the value of the ALTMEMPHY
ctl_cal_success output. Writing to this bit has
no effect.
This bit reports the value of the ALTMEMPHY
ctl_cal_fail output. Writing to this bit has no
effect.
Writing a 1 to this bit asserts the ctl_cal_req
signal to the ALTMEMPHY megafunction. Writing a
0 to this bit deaaserts the signal, and the
ALTMEMPHY megafunction will then initiate its
calibration sequence.
Reserved for future use.
Writing a 1 to any of the bits in this register causes
the appropriate ctl_mem_clk_disable signal to
the ALTMEMPHY megafunction to be asserted,
which disables the memory clock outputs. Writing
a 0 to this register deasserts the signal and
re-enables the memory clocks. The ALTMEMPHY
megafunction supports up to 6 individual memory
clocks, each bit will represent each individual clock.
Reserved for future use.
The number of idle clock cycles after which the
controller should place the memory into
power-down mode. The controller is considered
to be idle if there are no commands in the
command queue. Setting this register to 0
disables the auto power-down mode. The default
value of this register depends on the values set
during the generation of the design.
This bit indicates that the memory is in
power-down state.
c
You must not use this register
during the ALTMEMPHY
megafunction calibration. You
must wait until the
CAL_SUCCESS or CAL_FAIL
register shows a value of 1.
External Memory Interface Handbook Volume 3
Description
Description
Table 7–6
using
7–21