IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 159

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers II
DDR3 High-Performance Controllers II
December 2010 Altera Corporation
The following sequence corresponds with the numbered items in
1. The write leveling stage.
2. The write leveling coarse phase sweep.
3. Fine T9/T10 delay chain sweep.
4. The write burst training pattern.
5. Three training patterns available at different addresses—zeroes, ones, and mixed.
6. The read path setup starts with the first operation, read deskew.
7. The read path deskew increases capture margin.
8. The write deskew stage; patterns written to RAM and read back.
9. The write datapath setup; data written to DRAM to determine latency.
10. Advertise read and write latency stage.
11. Tracking setup stage to set up mimic window.
12. Calibration successful on user mode.
This section discusses the following timing diagrams for HPC II:
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“Half-Rate Read (Burst-Aligned Address)”
“Half-Rate Write (Burst-Aligned Address)”
“Half-Rate Read (Non Burst-Aligned Address)”
“Half-Rate Write (Non Burst-Aligned Address)”
“Half-Rate Read With Gaps”
“Half-Rate Write With Gaps”
“Half-Rate Write Operation (Merging Writes)”
“Write-Read-Write-Read Operation”
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
Figure
9–7:
9–13