IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 95

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Block Description
Figure 6–1. DDR3 SDRAM HPC Block Diagram
December 2010 Altera Corporation
local_powerdn_ack
local_self_rfsh_ack
local_powerdn_req
local_self_rfsh_req
local_autopch_req
local_refresh_ack
local_refresh_req
local_rdata_valid
local_burstbegin
local_wdata_req
local_write_req
local_init_done
local_read_req
The high-performance controller (HPC) architecture instantiates encrypted control
logic and the ALTMEMPHY megafunction. The controller accepts read and write
requests from the user on its local interface, using either the Avalon-MM interface
protocol or the native interface protocol. It converts these requests into the necessary
SDRAM commands, including any required bank management commands. Each read
or write request on the Avalon-MM or native interface maps to one SDRAM read or
write command.
The half-rate DDR3 SDRAM HPC accepts requests of size 1 or 2 on the local interface.
If you request a burst size of 1, the controller issues a memory burst of 4 using the
DDR3 SDRAM on-the-fly burst chop (waits for two cycles before issuing the next read
or write command). If you request a burst size of 2, the controller issues a memory
burst of 8 (issues the next read or write command back to back). Requests of size 2 on
the local interface produce better throughput because DDR3 SDRAMs cannot accept
back-to-back bursts of size 4.
The bank management logic in the controller keeps a row open in every bank in the
memory system. For example, a controller configured for a dual-rank, 8-bank DDR3
SDRAM DIMM keeps an open row in each of the 16 banks. The controller allows you
to request an auto-precharge read or auto-precharge write, allowing control over
whether to keep that row open after the request. You can achieve maximum efficiency
when you issue reads and writes to the same bank, with the last access to that bank
being an auto-precharge read or write. The controller does not do any access
reordering.
Figure 6–1 on page 6–1
local_wdata
local_ready
local_rdata
local_size
local_be
(Encrypted)
Control
Logic
shows the top-level block diagram of the DDR3 SDRAM HPC.
Performance Controller
DDR3 SDRAM High-
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
ALTMEMPHY
Megafunction
High-Performance Controller
6. Functional Description—
External Memory Interface Handbook Volume 3
mem_a
mem_ba
mem_cas_n
mem_cke
mem_clk
mem_clk_n
mem_cs_n
mem_dm
mem_dq
mem_dqs
mem_dqsn
mem_odt
mem_ras_n
mem_reset_n
mem_we_n