IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 50

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–4
Simulating the Design
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
f
6. Select your required I/O driver strength (derived from your board simulation) to
7. To compile the design, on the Processing menu, click Start Compilation.
After you have compiled the example top-level file, you can perform RTL simulation
or program your targeted Altera device to verify the example top-level file in
hardware.
During system generation, SOPC Builder optionally generates a simulation model
and testbench for the entire system, which you can use to easily simulate your system
in any of Altera's supported simulation tools. The MegaWizard also generates a set of
ModelSim
functional simulation models, and plain-text RTL design files that describe your
system in the ModelSim simulation software (refer to
For more information about simulating SOPC Builder systems, refer to
the Quartus II Handbook and
more information about how to include your board simulation results in the Quartus
II software and how to assign pins using pin planners, refer to
Tutorials
In ALTMEMPHY variations for DDR3 SDRAM with leveling and without
leveling interfaces, you have the following three simulation options:
■
■
ensure that you correctly drive each signal or ODT setting and do not suffer from
overshoot or undershoot.
Skip calibration—performs a static setup of the ALTMEMPHY megafunction to
skip calibration and go straight into user mode.
Available for ×4 and ×8 DDR3 SDRAM. Skip calibration simulation is supported
for 300 MHz through 400 MHz. There is no calibration in this simulation mode. As
no phase calibration is performed, there must be no delays in the testbench.
The ALTMEMPHY megafunction is statically configured to provide the correct
write and read latencies. Skip calibration provides the fastest simulation time for
DDR3 SDRAM interfaces. Use the generated or vendor DDR3 SDRAM simulation
models for this simulation option.
Skip calibration simulation between 300 MHz and 400 MHz supports CAS latency
of 6 and a CAS write latency of 5.
1
1
Quick calibration—performs a calibration on a single pin and chip select.
Available for ×4 and ×8 DDR3 SDRAM. In quick calibration simulation mode, the
sequencer only does clock cycle calibration. So there must be no delays (DDR3
DIMM modeling for example) in the testbench, because no phase calibration is
performed. Quick calibration mode can be used between 300 MHz and 533 MHz.
Both the generated or vendor DDR3 SDRAM simulation models support burst
length on-the-fly changes during the calibration sequence.
section in volume 6 of the External Memory Interface Handbook.
The additive latency and registered DIMMs must be disabled.
Skip calibration is unavailable for DDR3 RDIMMs.
®
Tcl scripts and macros that you can use to compile the testbench, IP
AN 351: Simulating Nios II Embedded Processor
“Generated Files” on page
Chapter 4: Compiling and Simulating
December 2010 Altera Corporation
ALTMEMPHY Design
Simulating the Design
volume 4
Designs. For
2–6).
of