IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 79

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—ALTMEMPHY
ALTMEMPHY Signals
Table 5–4. AFI Signals (Part 3 of 3)
Table 5–5. Other Interface Signals (Part 1 of 4)
December 2010 Altera Corporation
ctl_rdata_valid
ctl_rlat
Address and Command Interface
ctl_addr
ctl_ba
ctl_cke
ctl_cs_n
ctl_odt
ctl_ras_n
ctl_we_n
ctl_cas_n
ctl_rst_n
Calibration Control and Status Interface
ctl_mem_clk_disable
ctl_cal_success
ctl_cal_fail
ctl_cal_req
ctl_cal_byte_lane_
sel_n
Note to
(1) Refer to
External DLL Signals
dqs_delay_ctrl_expor
t
Signal Name
Table
Signal Name
Table 5–6
5–3:
for parameter descriptions.
Output
Type
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Input
Input
Type
DQS_DELA
Y_CTL_WI
DTH
DWIDTH_RATIO/2
READ_LAT_WIDTH
MEM_IF_ROWADDR_WIDTH
× DWIDTH_RATIO / 2
MEM_IF_BANKADDR_WIDT
H × DWIDTH_RATIO / 2
MEM_IF_CS_WIDTH ×
DWIDTH_RATIO / 2
MEM_IF_CS_WIDTH
×DWIDTH_RATIO / 2
MEM_IF_CS_WIDTH ×
DWIDTH_RATIO / 2
DWIDTH_RATIO / 2
DWIDTH_RATIO / 2
DWIDTH_RATIO / 2
DWIDTH_RATIO / 2
MEM_IF_CLK_PAIR_
COUNT
1
1
1
MEM_IF_DQS_WIDTH ×
MEM_CS_WIDTH
Width
Width
Allows sharing DLL in this ALTMEMPHY instance with another
ALTMEMPHY instance. Connect the dqs_delay_ctrl_export port
on the ALTMEMPHY instance with a DLL to the
dqs_delay_ctrl_import port on the other ALTMEMPHY instance.
(1)
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Read data valid indicating valid read data on
ctl_rdata. This signal is two-bits wide (as only
half-rate or DWIDTH_RATIO = 4 is supported) to
allow controllers to issue reads and writes that are
aligned to either the half-cycle of the half-rate clock.
Contains the number of clock cycles between the
assertion of ctl_doing_rd and the return of valid
read data (ctl_rdata). This signal is unused by
the Altera high-performance controllers.
Row address from the controller.
Bank address from the controller.
Clock enable from the controller.
Chip select from the controller.
On-die-termination control from the controller.
Row address strobe signal from the controller.
Write enable.
Column address strobe signal from the controller.
Reset from the controller.
When asserted, mem_clk and mem_clk_n are
disabled.
A 1 indicates that calibration was successful.
A 1 indicates that calibration has failed.
When asserted, a new calibration sequence is
started. Currently not supported.
Indicates which DQS groups should be calibrated.
Not supported.
Description
External Memory Interface Handbook Volume 3
Description
5–27