IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 153
![IP CORE Renewal Of IP-HPMCII](/photos/24/19/241941/4696148_sml.jpg)
IPR-HPMCII
Manufacturer Part Number
IPR-HPMCII
Description
IP CORE Renewal Of IP-HPMCII
Manufacturer
Altera
Datasheet
1.IP-HPMCII.pdf
(176 pages)
Specifications of IPR-HPMCII
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Arria II GX, HardCopy III, Stratix III, Stratix IV
Core Architecture
FPGA
Core Sub-architecture
Arria, HardCopy, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers
December 2010 Altera Corporation
The following sequence corresponds with the numbered items in
1. The user logic requests write by asserting the local_write_req signal.
2. The local_ready signal is asserted, indicating that the controller has accepted the
3. The data written to the memory for the write command.
4. The write (WR) command on the command bus.
5. The valid write data on the ctl_wdata signal.
6. The valid data on the mem_dq signal goes to the controller.
request.
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
Figure
9–4:
9–7
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