IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 138

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–22
Table 7–13. Address 0x110 Controller Status and Configuration Register (Part 2 of 2)
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
21:20
24:23
30:24
Bit
17
18
19
22
SELF_RFSH
SELF_RFSH-ACK
Reserved
ADDR_ORDER
REGDIMM
CTRL_DRATE
Reserved
Name
Default
00
00
0
0
0
0
0
Access
RW
RW
RW
RO
RO
—
—
Chapter 7: Functional Description—High-Performance Controller II
Setting this bit, or asserting the
local_self_rfsh signal, causes the memory
to go into self-refresh state.
This bit indicates that the memory is in
self-refresh state.
Reserved for future use.
00 - Chip, row, bank, column.
01 - Chip, bank, row, column.
10 - Reserved for future use.
11 - Reserved for future use.
Setting this bit to 1 enables REGDIMM support
in controller.
These bits represent controller date rate:
00 - Full rate.
01 - Half rate.
10 - Reserved for future use.
11 - Reserved for future use.
Reserved for future use.
December 2010 Altera Corporation
Description
Register Maps Description