IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 142

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–26
Table 7–22. Address 0x131 ECC Status Register (Part 2 of 2)
Table 7–23. Address 0x132 ECC Error Address Register
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
23:16
31:24
15:8
31:0
Bit
Bit
SBE_COUNT
DBE_COUNT
Reserved
ERR_ADDR
Name
Name
Default
Default
0
0
0
0
Access
Access
RO
RO
RO
—
Chapter 7: Functional Description—High-Performance Controller II
Reports the number of single-bit errors that have
occurred since the status register counters were
last cleared.
Reports the number of double-bit errors that
have occurred since the status register counters
were last cleared.
Reserved for future use.
The address of the most recent ECC error. This
address contains concatenation of chip, bank,
row, and column addresses.
Description
Description
December 2010 Altera Corporation
Register Maps Description