IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 136

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–20
Table 7–10. Address 0x005 Mode Register 0-1 (Part 2 of 2)
Table 7–11. Address 0x006 Mode Register 2-3
External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
25:23
31:29
15:11
17:16
31:19
10:9
Bit
Bit
2:0
5:3
22
26
27
28
18
6
7
8
RTT
RTT/WL/OCD
DQS#
TDQS/RDQS
QOFF
Reserved
Reserved
CWL
ASR
SRT/ET
Reserved
RTT_WR
Reserved
MPR_RF
MPR
Reserved
Name
Name
Default
Default
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
—
—
—
—
—
Chapter 7: Functional Description—High-Performance Controller II
Not used by the controller, but you can set and
program into the memory device mode register.
Reserved for future use.
Reserved for future use.
CAS write latency setting. The default value for
these bits is set by the MegaWizard CAS Write
Latency setting for your controller instance. You
must set this value in the CSR interface register
map 0x126
Not used by the controller, but you can set and
program into the memory device mode register.
Reserved for future use.
Not used by the controller, but you can set and
program into the memory device mode register.
Reserved for future use.
Not used by the controller, but you can set and
program into the memory device mode register.
Reserved for future use.
(Table
7–20) as well.
Description
Description
December 2010 Altera Corporation
Register Maps Description