IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 139

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Functional Description—High-Performance Controller II
Register Maps Description
Table 7–14. Address 0x120 Memory Address Size Register 0
Table 7–15. Address 0x121 Memory Address Size Register 1
Table 7–16. Address 0x122 Memory Address Size Register 2
December 2010 Altera Corporation
19:16
23:20
31:24
15:8
31:0
31:8
Bit
7:0
Bit
Bit
7:0
Column address
width
Row address width
Bank address width
Chip select address
width
Reserved
Data width
representation
(word)
Chip select
representation
Reserved
Name
Name
Name
Default
Default
Default
—
—
—
—
—
—
0
0
Access
Access
Access
RW
RW
RW
RW
RW
RW
—
—
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
The number of column address bits for the
memory devices in your memory interface. The
range of legal values is 7-12.
The number of row address bits for the memory
devices in your memory interface. The range of
legal values is 12-16.
The number of bank address bits for the memory
devices in your memory interface. The range of
legal values is 2-3.
The number of chip select address bits for the
memory devices in your memory interface. The
range of legal values is 0-2. If there is only one
single chip select in the memory interface, set
this bit to 0.
Reserved for future use.
The number of DQS bits in the memory interface.
This bit can be used to derive the width of the
memory interface by multiplying this value by the
number of DQ pins per DQS pin (typically 8).
The number of chip select in binary
representation.
For example, a design with 2 chip selects has the
value of 00000011.
Reserved for future use.
External Memory Interface Handbook Volume 3
Description
Description
Description
7–23