IPR-HPMCII Altera, IPR-HPMCII Datasheet - Page 69

• Manufacturer Part Number: IPR-HPMCII
• Description: IP CORE Renewal Of IP-HPMCII
• Manufacturer: Altera

Specifications of IPR-HPMCII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—ALTMEMPHY
Block Description
Table 5–2. DDR3 SDRAM Clocking Stratix IV and Stratix III Devices (Part 2 of 2)
Figure 5–7. ALTMEMPHY Reset Management Block for Arria II GX Devices
December 2010 Altera Corporation
Another
system
clock
ac_clk_1x
Notes to
(1) In full-rate designs a _1x clock may run at full-rate clock rate.
(2) This clock should be of the same clock network clock as the resync_clk_1x clock.
Clock Name
edge detect and
reset_ request_n
Table
reset counter
clk_div_reset_ams_n
Optional
5–2:
(1)
D
CLR
SET
global_reset_n
pll_ref_clk
Q
Q
The phase-shift inputs on the PLL perform the PLL reconfiguration. The PLL
reconfiguration megafunction is not required.
Reset Management
Figure 5–8
the DDR3 SDRAM PHY. You can use the pll_ref_clk input to feed the optional
reset_request_n edge detect and reset counter module. However, this requires the
pll_ref_clk signal to use a global clock network resource.
There is a unique reset metastability protection circuit for the clock divider circuit
because the phy_clk domain reset metastability protection registers have fan-in from
the soft_reset_n input so these registers cannot be used.
C6
soft_reset_n
Postscale
clk_div_reset_ams_n_r
Counter
D
CLR
SET
Q
Q
clk_divider_reset_n
and
Set in the
GUI
(Degrees)
pll_reconfig_reset_n
phy_clk
reset_n
Phase
Divider
Circuit
Figure 5–9
scan_clk
clk
pll_reconfig_reset_ams_n
D
Half-Rate
CLR
SET
Q
Q
Clock
show the main features of the reset management block for
Rate
pll_reprogram_request_long_pulse
D
SET
CLR
Q
Q
Regional
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
reprogram_
Network
D
CLR
SET
Clock
request
Type
seq_pll_start_reconfig
Q
Q
pll_
pll_reset
D
pll_reconfig_
CLR
SET
ams_n_r
reset_
phasestep
phaseupdown
scan_clk
refclk
areset
(active HIGH)
Q
Q
global_or_soft_reset_n
Address and command clock.
PLL
locked
External Memory Interface Handbook Volume 3
pll_new_dir
D
CLR
SET
pll_locked
c0
Q
Q
reset_master_ams
phy_internal_reset_n
Notes
D
CLR
SET
Q
Q
global_pre_clear
D
CLR
SET
Q
Q
Reset
Pipes
reset_request_n
phy_clk_out
PHY resets
5–17