EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 130

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
UART_TxD
Baud Rate
IR_TxD
7-clock
Transmit
Receive
Clock
delay
For more information on the UART and its Baud Rate Generator, see
nous Receiver/Transmitter on page
The data to be transmitted via the IR transceiver is first sent to UART0. The UART
transmit signal (TxD) and Baud Rate Clock are used by the infrared encoder/decoder to
generate the modulation signal (IR_TXD) that drives the infrared transceiver. Each UART
bit is 16-clocks wide. If the data to be transmitted is a logical 1 (High), the IR_TXD signal
remains Low (0) for the full 16-clock period. If the data to be transmitted is a logical 0, a
3-clock High (1) pulse is output following a 7-clock Low (0) period. Following the
3-clock High pulse, a 6-clock Low pulse completes the full 16-clock data period. Data
transmission is illustrated in
should be disabled by clearing the IR_RXEN bit in the IR_CTL reg to 0. This prevents
transmitter to receiver cross-talk.
Data received from the IR transceiver via the IR_RXD signal is decoded by the infrared
encoder/decoder and passed to the UART. The IR_RXEN bit in the IR_CTL register must
be set to enable the receiver decoder. The SIR data format uses half duplex communica-
tion therefore the UART should not be allowed to transmit while the receiver decoder is
enabled. The UART Baud Rate Clock is used by the infrared encoder/decoder to generate
the demodulated signal (RxD) that drives the UART. Each UART bit is 16-clocks wide. If
the data to be received is a logical 1 (High), the IR_RXD signal remains High (1) for the
full 16-clock period. If the data to be received is a logical 0, a 3-clock Low (0) pulse is
Start Bit = 0
16-clock
period
3-clock
pulse
Figure 25. Infrared Data Transmission
Data Bit 0 = 1
Figure
104.
25. During data transmission, the IR receive function
Data Bit 1 = 0
Data Bit 2 = 1
Product Specification
Infrared Encoder/Decoder
Universal Asynchro-
Data Bit 3 = 1
124