EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 160

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
accessed in SLAVE mode, the I
enters MASTER mode when the bus is released. The STA bit is automatically cleared after
a START condition is set. Writing a 0 to this bit produces no effect.
If the Master Mode Stop bit (STP) is set to 1 in MASTER mode, a STOP condition is
transmitted on the I
as if a STOP condition is received, but no STOP condition is transmitted. If both STA and
STP bits are set, the I
and then transmit the START condition. The STP bit is cleared automatically. Writing a 0
to this bit produces no effect.
The I
I
set to 1 and the IEN bit is also set, an interrupt is generated. When IFLG is set by the I
the Low period of the I
When a 0 is written to IFLG, the interrupt is cleared and the I
When the I
acknowledge clock pulse on the I
•
•
•
When AAK is cleared to 0, a NACK is sent when a data byte is received in MASTER or
SLAVE mode. If AAK is cleared to 0 in the Slave Transmitter mode, the byte in the
I2C_DR register is assumed to be the final byte. After this byte is transmitted, the I
block enter states
its slave address unless AAK is set. See
Table 84. I
Bit
Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
2
C states is entered. The only state that does not set the IFLG bit is state F8h. If IFLG is
Either the whole of a 7-bit slave address or the first or second byte of a 10-bit slave ad-
dress is received
The general call address is received and the General Call Enable bit in I2C_SAR is set
to 1
A data byte is received while in MASTER or SLAVE modes
2
C Interrupt Flag (IFLG) is set to 1 automatically when any of 30 of the possible 31
2
2
C Acknowledge bit (AAK) is set to 1, an Acknowledge is sent during the
C Control Registers
C8h
2
C bus. If the STP bit is set to 1 in slave move, the I
2
, then returns to the idle state. The I
C block first transmits the STOP condition (if in MASTER mode)
2
C bus clock line is stretched and the data transfer is suspended.
R/W
7
0
2
C completes the data transfer in SLAVE mode and then
2
C bus if:
R/W
6
0
(I2C_CTL = 00CBh)
Table
R/W
5
0
84.
R/W
4
0
2
C module does not respond to
R/W
3
0
2
C clock line is released.
Product Specification
R/W
2
0
I
2
2
C module operates
C Serial I/O Interface
R
1
0
2
C
R
0
0
2
C,
154