EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 57

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
Caution:
WAIT States
WAIT Input Signal
If the WAIT pin is to be driven by an external device, the corresponding Chip Select for the
If all the above conditions are met to generate an I/O Chip Select, then the following
actions occur:
•
•
•
For each of the Chip Selects, programmable WAIT states can be asserted to provide
external devices with additional clock cycles to complete their Read or Write operations.
The number of WAIT states for a particular Chip Select is controlled by the 3-bit field
CSx_WAIT (CSx_CTL[7:5]). The WAIT states can be independently programmed to
provide 0 to 7 WAIT states for each Chip Select. The WAIT states idle the CPU for the
specified number of system clock cycles.
Similar to the programmable WAIT states, an external peripheral drives the WAIT input
pin to force the CPU to provide additional clock cycles to complete its Read or Write oper-
ation. Driving the WAIT pin Low stalls the CPU. The CPU resumes operation on the first
rising edge of the internal system clock following de-assertion of the WAIT pin.
device must be programmed to provide at least one WAIT state. Due to input sampling of
the WAIT input pin (see
external peripheral sufficient time to assert the WAIT pin. It is recommended that the cor-
responding Chip Select for the external device be programmed to provide the maximum
number of WAIT states (seven).
Wait
Pin
The appropriate Chip Select—CS0, CS1, CS2, or CS3—is asserted (driven Low).
IORQ is asserted (driven Low).
Depending upon the instruction, either RD or WR is asserted (driven Low).
System Clock
D
Q
Figure 5. Wait Input Sampling Block Diagram
Figure
5), one programmable WAIT state is required to allow the
eZ80
CPU
Chip Selects and Wait States
Product Specification
eZ80L92 MCU
51