EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 60
EZ80L92AZ050SG
Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ050SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG
EZ80L92AZ050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80L92AZ050SG
Manufacturer:
Everlight
Quantity:
12 000
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Table 15. Z80
PS013014-0107
STATE T1
STATE T2
STATE T3
The Write cycle begins in State T1. The CPU drives the address onto the address bus, the
associated Chip Select signal is asserted.
During State T2, the WR signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one eZ80
system clock cycle prior to the end of State T2, additional WAIT states (T
until the WAIT pin is driven High.
During State T3, no bus signals are altered.
®
During Write operations, Z80 Bus Mode employs 3 states (T1, T2, and T3) as described in
Table
Z80 Bus Mode Read and Write timing is illustrated in
Mode states can be configured for 1 to 15 eZ80 system clock cycles. In these figures, each
Z80 Bus Mode state is two eZ80 system clock cycles in duration.
also illustrate the assertion of 1 WAIT state (T
Z80 Bus Mode cycle.
Bus Mode Write States
15.
WAIT
) by the external peripheral during each
Figure 7
and
Chip Selects and Wait States
Product Specification
Figure 7
Figure
WAIT
eZ80L92 MCU
8. The Z80 Bus
and
) are asserted
Figure 8
54
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