EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 44

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

General-Purpose Input/Output
PS013014-0107
GPIO Operation
The eZ80L92 MCU features 24 General-Purpose Input/Output (GPIO) pins. The GPIO
pins are assembled as three 8-bit ports — Port B, Port C, and Port D. All port signals can
be configured for use as either inputs or outputs. In addition, all the port pins can be used
as vectored interrupt sources for the eZ80 CPU.
The GPIO operation is same for all 3 GPIO ports (Ports B, C, and D). Each port features
eight GPIO port pins. The operating mode for each pin is controlled by four bits that are
divided between four 8-bit registers. These GPIO mode control registers are:
•
•
•
•
where x is B, C, or D representing any of the three GPIO ports B, C, or D. The mode for
each pin is controlled by setting each register bit pertinent to the pin to be configured. For
example, the operating mode for Port B Pin 7 (PB7), is set by the values contained in
PB_DR[7], PB_DDR[7], PB_ALT1[7], and PB_ALT2[7].
The combination of the GPIO control register bits allows individual configuration of each
port pin for nine modes. In all modes, reading of the Port x Data register returns the
sampled state, or level, of the signal on the corresponding pin.
each port signal based upon these four register bits. After a RESET event, all GPIO port
pins are configured as standard digital inputs, with interrupts disabled.
Port x Data Register (Px_DR)
Port x Data Direction Register (Px_DDR)
Port x Alternate Register 1 (Px_ALT1)
Port x Alternate Register 2 (Px_ALT2)
Table 6
General-Purpose Input/Output
Product Specification
lists the function of
eZ80L92 MCU
38