MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 107

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

primary PCI clock input or an external oscillator. For background information regarding the e500 core
refer to the following documents:
The following is a brief list of some of the key features of the e500 core complex:
Freescale Semiconductor
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The e500 core family reference manual
PowerPC™ e500 Application Binary Interface User's Guide
EREF: A Programmer's Reference Manual for Freescale Book E Processors—this book will be
replaced by EREF: A Programmer’s Reference Manual for Freescale Embedded Processors
(Including the e200, e500, and e700 Families)
Implements full Book E 32-bit architecture
Implements additional instructions, registers, and interrupts defined by auxiliary processing units
(APUs). The SPE APU provides an extensive instruction set for 64-bit vector integer and fractional
operations. The embedded floating-point APUs provide vector single-precision instructions that
operate on operands comprised of two 32-bit elements; the single-precision scalar instructions use
only the bottom word. The double-precision floating-point APU provides scalar (64-bit)
double-precision floating-point instructions that use the 64-bit GPRs.
L1 cache structure
— 32-Kbyte, 32-byte line, eight-way set-associative instruction cache
— 32-Kbyte, 32-byte line, eight-way set-associative data cache
— 1.5-cycle cache array access, 3-cycle load-to-use latency
— Pseudo-LRU replacement algorithm
— Copy-back data cache
Dual-dispatch superscalar
Precise exception handling
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
The e500 defines features that are not implemented on this device. It also
generally defines some features that this device implements more
specifically. An understanding of these differences can be critical to ensure
proper operations.
The SPE APU and double-precision floating-point APU functionality is
implemented in all PowerQUICC III devices. However, these instructions
will not be supported in devices subsequent to PowerQUICC III. Freescale
strongly recommends that use of these instructions be confined to libraries
and device drivers. Customer software that uses SPE, double-precision
floating-point, or embedded floating-point APU instructions at the
assembly level or that uses SPE intrinsics will require rewriting for upward
compatibility with next-generation PowerQUICC devices.
Freescale offers a libcfsl_e500 library that uses SPE instructions. Freescale
will also provide libraries to support next-generation PowerQUICC devices.
NOTE
NOTE
Overview
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