MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 910

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 15-147
15-178
Offset Bits
0–1
typedef unsigned short uint_16; /* choose 16-bit native type */
typedef unsigned int uint_32; /* choose 32-bit native type */
typedef struct rxbd_struct {
} rxbd;
0
1
2
3
4
5
6
7
uint_16 flags;
uint_16 length;
uint_32 bufptr;
describes the fields of the RxBD.
Name
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
RO1
W
—
M
E
F
L
I
Empty, written by the eTSEC (when cleared) and by the user (when set).
0 The data buffer associated with this BD is filled with received data, or data reception is aborted due
1 The data buffer associated with this BD is empty, or reception is currently in progress.
Receive software ownership bit.
This field is reserved for use by software. This read/write bit is not modified by hardware, nor does its
value affect hardware.
Wrap, written by user.
0 The next buffer descriptor is found in the consecutive location.
1 The next buffer descriptor is found at the location defined in RBASE.
Interrupt, written by user.
0 No interrupt is generated after this buffer is serviced.
1 IEVENT[RXB] or IEVENT[RXF] are set after this buffer is serviced. This bit can cause an interrupt
Last in frame, written by the eTSEC.
0 The buffer is not the last in a frame.
1 The buffer is the last in a frame.
First in frame, written by the eTSEC.
0 The buffer is not the first in a frame.
1 The buffer is the first in a frame.
Reserved
Miss, written by the eTSEC. (This bit is valid only if the L-bit is set and eTSEC is in promiscuous mode.)
This bit is set by the eTSEC for frames that were accepted in promiscuous mode, but were flagged as
a “miss” by the internal address recognition; thus, while in promiscuous mode, the user can use the
M-bit to quickly determine whether the frame was destined to this station.
0 The frame was received because of an address recognition hit.
1 The frame was received because of promiscuous mode.
Table 15-147. Receive Buffer Descriptor Field Descriptions
to an error condition. The status and length fields have been updated as required.
if enabled (IMASK[RXBEN] or IMASK[RXFEN]). If the user wants to be interrupted only if RXF
occurs, then the user must disable RXB (IMASK[RXBEN] is cleared) and enable RXF
(IMASK[RXFEN] is set).
Figure 15-138. Mapping of RxBDs to a C Data Structure
Description
Freescale Semiconductor