MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 357

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.4.1.19
The memory data path error injection mask high register is shown in
Table 9-25
9.4.1.20
The memory data path error injection mask low register is shown in
Table 9-26
Freescale Semiconductor
0–31
0–31
Bits
Bits
Offset 0xE00
Offset 0xE04
Reset
Reset
W
W
Figure 9-21. Memory Data Path Error Injection Mask Low Register (DATA_ERR_INJECT_LO)
R
Figure 9-20. Memory Data Path Error Injection Mask High Register (DATA_ERR_INJECT_HI)
R
Name
Name
EIMH Error injection mask high data path. Used to test ECC by forcing errors on the high word of the data path.
EIML
0
0
describes the DATA_ERR_INJECT_HI fields.
describes the DATA_ERR_INJECT_LO fields.
Memory Data Path Error Injection Mask High (DATA_ERR_INJECT_HI)
Memory Data Path Error Injection Mask Low (DATA_ERR_INJECT_LO)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Setting a bit causes the corresponding data path bit to be inverted on memory bus writes.
Error injection mask low data path. Used to test ECC by forcing errors on the low word of the data path. Setting
a bit causes the corresponding data path bit to be inverted on memory bus writes.
Table 9-26. DATA_ERR_INJECT_LO Field Descriptions
Table 9-25. DATA_ERR_INJECT_HI Field Descriptions
All zeros
All zeros
EIMH
EIML
Description
Description
Figure
Figure
9-21.
9-20.
Access: Read/Write
Access: Read/Write
DDR Memory Controller
31
31
9-33