MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 174

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
4.4.3.7
The CPU boot configuration input, shown in
is sampled low at reset, the e500 core is prevented from fetching boot code until configuration by an
external master is complete. The external master frees the CPU to boot by setting EEBPCR[CPU_EN] in
the ECM CCB port configuration register (EEBPCR). See
Register (EEBPCR),”
Note that the value latched on this signal during POR is accessible through the memory-mapped
PORBMSR (POR boot mode status register) described in
Register (PORBMSR).”
Note also that the value latched on this signal during POR affects the PCI agent lock mode (See
Section 17.3.2.19, “PCI Bus Function Register
Register (See
4-16
TSEC3_TXD[6:4]
Default (111)
Functional
Signal
CPU Boot Configuration
Section 18.3.10.18, “Configuration Ready
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reset Configuration
cfg_IO_ports[0:2]
for more information.
Name
Table 4-14. I/O Port Selection (continued)
(Binary)
Value
110
111
Table
(PBFR).”) and the PCI Express Configuration Ready
All three PCI Express ports active
PCI Express 1:
RX lane[0:3] → SD1_RX[0:3],
TX lane[0:3] → SD1_TX[0:3]
PCI Express 2:
RX lane[0:3] → SD1_RX[4:7],
TX lane[0:3] → SD1_TX[4:7]
PCI Express 3:
RX lane[0] → SD2_RX[0],
TX lane[0] → SD2_TX[0]
SGMII ports powered down
All three PCI Express ports active
PCI Express 1:
RX lane[0:3] → SD1_RX[0:3],
TX lane[0:3] → SD1_TX[0:3]
PCI Express 2:
RX lane[0:3] → SD1_RX[4:7],
TX lane[0:3] → SD1_TX[4:7]
PCI Express 3:
RX lane[0] → SD2_RX[0],
TX lane[0] → SD2_TX[0]
SGMII ports active
SGMII:
RX lane[0:1] → SD2_RX[2:3]
TX lane[0:1] → SD2_TX[2:3]
4-15, specifies the boot configuration mode. If LA27
Register—0x4B0.”).
Section 8.2.1.2, “ECM CCB Port Configuration
Section 19.4.1.2, “POR Boot Mode Status
Meaning
Freescale Semiconductor