MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1250

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Debug Features and Watchpoint Facility
21.3.2.4
The trace buffer transaction mask register (TBTMR) shown in
types to monitor. Each bit in the TBTMR represents a transaction type on the selected interface. The
transaction associated with any particular bit depends on the interface being monitored as specified by
TBCR1[IFSEL]. Note that the transactions used for defining trace buffer events are the same as those
defined for watchpoint monitor events. Thus,
each interface. Setting a bit enables a hit when this transaction is matched (provided all other match criteria
are met and TBCR0[TMD] is clear).
Different interfaces support different transaction types, and the same bit may represent different
transaction types depending on the interface.
Table 21-18
21.3.2.5
The trace buffer status register (TBSR) shown in
buffer.
21-20
Offset 0x058
Reset
0–31
Bits
Offset 0x05C
Reset
W
R
W
R
0
Name
TBTM Trace buffer transaction mask. Each bit corresponds to a transaction type as defined in
ACT TRIG STP WRAP
0
describes the TBTMR field.
Trace Buffer Transaction Mask Register (TBTMR)
Trace Buffer Status Register (TBSR)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
1
transaction associated with a bit depends on the interface being monitored. A value of 1 for a given mask bit
enables the matching of the transaction associated with that bit. These bits are meaningful only when
TBCR0[TMD]=0.
2
Figure 21-12. Trace Buffer Transaction Mask Register (TBTMR)
3
Figure 21-13. Trace Buffer Status Register (TBSR)
4
Table 21-18. TBTMR Field Descriptions
Table 21-12
Figure 21-13
All zeros
All zeros
TBTM
—
Description
defines the transaction types associated with
Figure 21-12
indicates the operational state of the trace
specifies which transaction
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Freescale Semiconductor
Access: Read/Write
C_INDX
Table
Access: Read/Write
21-12. The
31
31