MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 827

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.5.3.6.30 Transmit Deferral Packet Counter (TDFR)
Figure 15-81
Table 15-84
15.5.3.6.31 Transmit Excessive Deferral Packet Counter (TEDF)
Figure 15-82
Table 15-85
Freescale Semiconductor
20–31
0–19
Bits
Offset eTSEC1:0x2_46F4; eTSEC3:0x2_56F4
Reset
Offset
Reset
20–31
0–19
Bits
W
W
R
R
Name
TDFR
0
0
eTSEC1:0x2_46F8; eTSEC3:0x2_56F8
—
describes the fields of the TDFR register.
describes the fields of the TEDF register.
Name
TEDF
describes the definition for the TDFR register.
describes the definition for the TEDF register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 15-82. Transmit Excessive Deferral Packet Counter Register Definition
—
Reserved
Transmit deferral packet counter. Increments for each frame, which was deferred on its first transmission
attempt. This count does not include frames involved in collisions.
Figure 15-81. Transmit Deferral Packet Counter Register Definition
Reserved
an excessive period of time (3036 byte times).
Transmit excessive deferral packet counter. Increments for frames aborted which were deferred for
Table 15-84. TDFR Field Descriptions
Table 15-85. TEDF Field Descriptions
—
—
All zeros
All zeros
Description
Description
19 20
19 20
Enhanced Three-Speed Ethernet Controllers
TDFR
TEDF
Access: Read/Write
Access: Read/Write
15-95
31
31