MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 125

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 2
Memory Map
This chapter describes the MPC8544E memory map. An overview of the local address map is followed by
a description of how local access windows are used to define the local address map. The inbound and
outbound address translation mechanisms used to map to and from external memory spaces are described
next. Finally, the configuration, control, and status registers are described, including a complete listing of
all memory-mapped registers with cross references to the sections detailing descriptions of each.
2.1
The MPC8544E provides an extremely flexible local memory map. The local memory map refers to the
36-bit address space seen by the processor as it accesses memory and I/O space. DMA engines also see
this same local memory map. All memory accessed by the MPC8544E DDR SDRAM and local bus
memory controllers exists in this memory map, as do all memory-mapped configuration, control, and
status registers.
The local memory map is defined by a set of ten local access windows. Each of these windows maps a
region of memory to a particular target interface, such as the DDR SDRAM controller or the PCI
controller. Note that the local access windows do not perform any address translation. The size of each
window can be configured from 4 Kbytes to 32 Gbytes. The target interface is specified using the codes
shown in
Freescale Semiconductor
.
Table
Local Memory Map Overview and Example
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2-1.
1
PCI
PCI Express 2
PCI Express 1
PCI Express 3
Local bus
DDR SDRAM
The general intent of the Target Interface Codes is to
maintain consistency across PowerQUICC III family
devices.
Table 2-1. Target Interface Codes
Target Interface
Target Code
00000
00001
00010
00011
00100
01111
1
2-1