MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1070

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
18.3.3.3
The PCI Express PME and message interrupt enable register, shown in
detection of a message or a PME event to generate an interrupt, provided that the corresponding bit in the
PCI Express PME and message detect register is set.
Table 18-11
18-16
Offset 0x028
Reset
Reset
0–15
Bits
16
17
18
19
20
21
22
W
W
R
R
PTOIE PTATIE
ENL23IE Entered L2/L3 ready interrupt enable. When set and PEX_PME_MES_DR[ENL23]=1 will generate an
EXL23IE Exited L2/L3 ready interrupt enable. When set and PEX_PME_MES_DR[EXL23]=1 will generate an
16
PTATIE
HRDIE
0
PTOIE
LDDIE
Name
—
—
shows the fields of the PCI Express PME and message interrupt enable register.
PCI Express PME and Message Interrupt Enable Register
(PEX_PME_MES_IER)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
17
Reserved
PME turn off interrupt enable. When set and PEX_PME_MES_DR[PTO]=1 will generate an interrupt.
1 Enable PME_Turn_Off_message interrupt generation
0 Disable PME_Turn_Off message interrupt generation
PME To ack time-out interrupt enable. When set and PEX_PME_MES_DR[PTAT]=1 will generate an
interrupt.
1 Enable PME_TO_Ack time-out interrupt generation
0 Disable PME_TO_Ack time-out interrupt generation
interrupt.
1 Enable Entered_L2/L3 ready state interrupt generation
0 Disable Entered_L2/L3 ready state interrupt generation
interrupt.
1 Enable Exited_L2/L3 ready state interrupt generation
0 Disable Exited_L2/L3 ready state interrupt generation
Reserved
Hot reset detected interrupt enable. When set and PEX_PME_MES_DR[HRD]=1 will generate an
interrupt.
1 Enable hot reset state interrupt generation
0 Disable hot reset state interrupt generation
Link down detected interrupt enable. When set and PEX_PME_MES_DR[LDD]=1 will generate an
interrupt.
1 Enable link down state interrupt generation
0 Disable link down state interrupt generation
L23IE
EN
18
Figure 18-9. PCI Express PME and Message Interrupt Enable
Table 18-11. PEX_PME_MES_IER Field Descriptions
L23IE
EX
19
—
20
Register (PEX_PME_MES_IER)
HRDIE LDDIE
21
22
All zeros
All zeros
23 24
—
—
Description
AIONIE AIBIE AIOFIE PIONIE PIBIE PIOFIE ABPIE
25
26
Figure
27
18-9, allows for the
28
Freescale Semiconductor
29
Access: Read/Write
30
15
31