MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 46
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Figure
Number
5-9
5-10
6-1
6-2
6-3
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6-5
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6-8
6-9
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6-28
6-29
6-30
6-31
6-32
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6-34
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6-36
6-37
6-38
6-39
xlvi
Effective-to-Real Address Translation Flow......................................................................... 5-24
Effective-to-Real Address Translation Flow (e500v2) ......................................................... 5-25
Core Register Model ............................................................................................................... 6-2
Integer Exception Register (XER) .......................................................................................... 6-8
Condition Register (CR) ......................................................................................................... 6-9
Link Register (LR) ................................................................................................................ 6-11
Count Register (CTR) ........................................................................................................... 6-11
Machine State Register (MSR) ............................................................................................. 6-11
Processor ID Register (PIR).................................................................................................. 6-13
Processor Version Register (PVR) ........................................................................................ 6-13
System Version Register (SVR)............................................................................................ 6-14
Timer Control Register (TCR) .............................................................................................. 6-14
Timer Status Register (TSR) ................................................................................................. 6-15
Time Base Upper/Lower Registers (TBU/TBL)................................................................... 6-16
Decrementer Register (DEC) ................................................................................................ 6-16
Decrementer Auto-Reload Register (DECAR)..................................................................... 6-17
Save/Restore Register 0 (SRR0) ........................................................................................... 6-17
Save/Restore Register 1 (SRR1) ........................................................................................... 6-17
Critical Save/Restore Register 0 (CSRR0) ........................................................................... 6-17
Critical Save/Restore Register 1 (CSRR1) ........................................................................... 6-18
Data Exception Address Register (DEAR) ........................................................................... 6-18
Interrupt Vector Prefix Register (IVPR) ............................................................................... 6-18
Interrupt Vector Offset Registers (IVORn) ........................................................................... 6-18
Exception Syndrome Register (ESR).................................................................................... 6-19
Machine Check Save/Restore Register 0 (MCSRR0)........................................................... 6-20
Machine Check Save/Restore Register 1 (MCSRR1)........................................................... 6-20
Machine Check Address Register (MCAR).......................................................................... 6-21
Machine Check Address Register Upper (MCARU)............................................................ 6-21
Machine Check Syndrome Register (MCSR) ....................................................................... 6-21
Software-Use SPRs (SPRG0–SPRG7 and USPRG0)........................................................... 6-22
Branch Buffer Entry Address Register (BBEAR) ................................................................ 6-23
Branch Buffer Target Address Register (BBTAR)................................................................ 6-23
Branch Unit Control and Status Register (BUCSR) ............................................................. 6-24
Hardware Implementation-Dependent Register 0 (HID0).................................................... 6-25
Hardware Implementation-Dependent Register 1 (HID1).................................................... 6-26
L1 Cache Control and Status Register 0 (L1CSR0).............................................................. 6-28
L1 Cache Control and Status Register 1 (L1CSR1).............................................................. 6-29
L1 Cache Configuration Register 0 (L1CFG0)..................................................................... 6-30
L1 Cache Configuration Register 1 (L1CFG1)..................................................................... 6-31
Process ID Registers (PID0–PID2)....................................................................................... 6-32
MMU Control and Status Register 0 (MMUCSR0) ............................................................. 6-32
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figures
Title
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