MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 448
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Programmable Interrupt Controller
The internal in-service register (ISR) tracks all in-service interrupts. An interrupt is considered in-service
from the time its vector is read (through an IACK cycle) until the end of interrupt (EOI) register is written,
generating what the PIC considers an EOI signal.
10.4.1.1
Each interrupt source is assigned a priority value through its corresponding vector/priority register. Priority
values range from 0 to 15, where 15 is the highest. Interrupts are delivered only when the priority of the
interrupt source is greater than the current task priority. Therefore setting a source priority to zero inhibits
that interrupt.
The PIC services simultaneous interrupts occurring with the same priority according to the following
order:
For example, if MSG0, MSG2, and IPI0 all have the same priority and receive simultaneous interrupts,
they are serviced in the following order:
10.4.1.2
The CTPR is set by system software to indicate the relative importance of the task running on the
processor. The processor does not receive interrupts with a priority level equal to or lower than its current
task priority. Therefore setting the current task priority to 15 for a particular processor prevents the delivery
of any interrupt to the processor.
10.4.1.3
The PIC unit notifies the processor core of an interrupt by asserting the int signal. When the processor core
acknowledges the interrupt request by reading the interrupt acknowledge register (IACK) in the PIC unit,
the PIC returns the 16-bit vector associated with the interrupt source to the processor. The interrupt is then
considered to be in-service, and remains in-service until the processor performs a write to the PIC unit end
of interrupt register (EOI). Writing to the EOI is referred to as an EOI cycle.
10-50
1. MSG0–MSG3
2. MSI0–MSI7
3. IPI0–IPI3
4. Timer 0–timer 3
5. IRQ[0:11]/PCI INTx
6. Internal 0–internal 31
1. MSG0
2. MSG2
3. IPI0
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Interrupt Source Priority
Processor Current Task Priority
Interrupt Acknowledge
Freescale Semiconductor
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