MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1279

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
0x2_0E4C
0x2_0E08
0x2_0E20
0x2_0E24
0x2_0E28
0x2_0E40
0x2_0E44
0x2_0E48
0x2_0E50
0x2_0E54
0x2_0E58
0x148
0x10C
0x11C
0x13C
0x17C
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x130
0x134
0x138
0x140
0x144
0x180
Offset
–
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
L2ERRINJCTL—L2 error injection tag/ECC control register
L2CAPTDATAHI—L2 error data high capture register
L2CAPTDATALO—L2 error data low capture register
L2CAPTECC—L2 error syndrome register
L2ERRDET—L2 error detect register
L2ERRDIS—L2 error disable register
L2ERRINTEN—L2 error interrupt enable register
L2ERRATTR—L2 error attributes capture register
L2ERRADDRH—L2 error address capture register high
L2ERRADDRL—L2 error address capture register low
L2ERRCTL—L2 error control register
MR0—DMA 0 mode register
SR0—DMA 0 status register
ECLNDAR0—DMA 0 current link descriptor extended
address register
CLNDAR0—DMA 0 current link descriptor address register
SATR0—DMA 0 source attributes register
SAR0—DMA 0 source address register
DATR0—DMA 0 destination attributes register
DAR0—DMA 0 destination address register
BCR0—DMA 0 byte count register
ENLNDAR0—DMA 0 next link descriptor extended address
register
NLNDAR0—DMA 0 next link descriptor address register
ECLSDAR0—DMA 0 current list descriptor extended address
register
CLSDAR0—DMA 0 current list descriptor address register
ENLSDAR0—DMA 0 next list descriptor extended address
register
NLSDAR0—DMA 0 next list descriptor address register
SSR0—DMA 0 source stride register
DSR0—DMA 0 destination stride register
Reserved
MR1—DMA 1 mode register
DMA Controller Block Base Address: 0x2_1000
Table B-1. Memory Map (continued)
Register
DMA Registers
Complete List of Configuration, Control, and Status Registers
Access
Mixed
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
R
R
R
R
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
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B-13