MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 674

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Local Bus Controller
14.4.3.7.5
This parameter, controlled by LSDMR[RFRC], defines the earliest timing for an ACTIVATE or
REFRESH command after a REFRESH command to the same SDRAM device.
14.4.3.7.6
If the additional delay of any buffers placed on the command strobes (LSDRAS, LSDCAS, LSDWE, and
LSDA10), is endangering the device setup time, LSDMR[BUFCMD] should be set. Setting this bit causes
the memory controller to add LCRR[BUFCMDC] extra bus cycles to the assertion of SDRAM control
signals (LSDRAS, LSDCAS, LSDWE, and LSDA10) for each SDRAM command.
14-54
LSDDQM[0:3]
LSDDQM
LSDRAS
LSDCAS
LAD[0:31]
LSDWE
LSDRAS
LSDCAS
LSDWE
LCLK
LCS n
LALE
LAD
LCLK
LCS n
LALE
ZZZZZZ RAS ADD
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Refresh Recovery Interval (RFRC)
External Address and Command Buffers (BUFCMD)
Setup Cycle
ZZZZZZZZ
Command
XXXXXXXX
Figure 14-41. BUFCMD = 1, LCRR[BUFCMDC] = 2
Command (If Needed)
1111
PRECHARGE ALL
Figure 14-40. RFRC = 4 (6 Clock Cycles)
CAS ADD
PRETOACT = 3
XXXX
Setup Cycle
Command
AUTO REFRESH
D0
Command
1111
1111
D1
0000
D2
RFRC = 4 (6 Clocks)
D3
RAS ADD
XXXX
Freescale Semiconductor
ZZZZZZZZ
1111
ACTIVATE
Command
CAS ADD