MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 295

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 7-24
Table 7-21
Figure 7-25
Table 7-22
7.4
Data from an I/O master can be allocated into the L2 cache while simultaneously being written to memory.
External (stashed) writes can be performed from any I/O master. For example:
Freescale Semiconductor
Offset 0x2_0E54
Offset 0x2_0E58
16–23
24–31
Reset
Reset
8–15
Bits
0–7
•
•
•
W
W
R
R
Ethernet
PCI/PCI-Express
DMA
0
0
28–31
0–27
Bits
L2CTHRESH L2 cache threshold. Threshold value for the number of ECC single-bit errors that are detected before
L2CCOUNT L2 count. Counts ECC single-bit errors detected. If L2CCOUNT equals the ECC single-bit error
External Writes to the L2 Cache (Cache Stashing)
describes L2ERRADDRL[L2ADDRL].
describes L2ERRCTL fields.
shows the L2 error address capture register low (L2ERRADDRL).
shows the L2 error control register (L2ERRCTL).
Name
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
—
—
Figure 7-24. L2 Error Address Capture Register (L2ERRADDRL)
L2ADDRL
Reserved
reporting an error condition.
Reserved
trigger threshold, an error is reported if single-bit error reporting is enabled.
Name
—
Figure 7-25. L2 Error Control Register (L2ERRCTL)
7
Table 7-21. L2ERRADDRL Field Description
Table 7-22. L2ERRCTL Field Descriptions
8
Reserved
L2 address bits 0–3 corresponding to detected error
L2CTHRESH
—
All zeros
All zeros
15 16
Description
Description
—
23 24
L2 Look-Aside Cache/SRAM
L2CCOUNT
Access: Read/Write
Access: Read Only
27 28
L2ADDRH
7-25
31
31